| 摘要 |
1517927 Storage IGFETs SIEMENS AG 9 Sept 1975 [20 Sept 1974 12 Feb 1975 25 March 1975 5 June 1975 (2)] 36983/75 Heading H1K An N-channel volatile memory FET having an insulation-embedded floating gate over at least part of its source-drain channel (which channel is <10Á long) is so designed that it can can be programmed by charging the floating gate with hot electrons generated by the mechanism of channel injection. In a simple form of FET adapted to be programmed in this way, which has a channel length of #3Á, the floating gate extends between and overlaps the source and drain regions of N-type formed in a 3-10 Ohm.cm P/type substrate, and is in turn overlaid by an insulated control gate electrode. The channel is preferably constricted or underlies a local thickening of the gate insulation adjacent the drain to create a high field acceleration zone in which the hot electrons are generated. The device may be so constructed, e.g. by provision of an ion implanted P+ channel region as to be blocked for zero control gate bias with the floating gate unprogrammed, programming then causing a further increase in source-drain resistance. During programming the control gate is positively biased to facilitate injection into the floating gate. Erasure can be achieved, with the control gate negative or zero biased, by ultra-violet irradiation or by avalanching of the source or drain junction, but the preferred method is by removal of the stored electrons (to the source, drain or channel) by the Fowler-Nordheim tunnelling and/or gate surface effects, using a continuous erasing voltage or a train of fast rising pulses. This method is characterized by low power dissipation and thus allows simultaneous rapid erasure of all the FETs in an integrated matrix and is optimized by use of a 600 Š layer of silica as gate insulation. Suitable biasing of the control gate enables a positive charge to be left on the floating gate. Contamination of the gate insulation is reduced and useful life thus increased by arranging that the charging and erasure currents pass through different parts of it, e.g. adjacent drain and source respectively, and/or by using an erasing voltage which rises slowly, e.g. in 3 seconds to a peak value or a train of voltages of slowly increasing amplitude to avoid the hole discharge currents associated with avalanching. If the floating gate is so located that the drain gate capacitance exceeds the gate-source capacitance or is directly connected to the drain so that it is at drain potential channel injection is greatly enhanced and the control gate may even be dispensed with, as it may if the FET is conductive with with the floating gate uncharged. If the capacity between the two gates is made high relative to that between the floating gate and the channel lower erase voltages may be used. In further embodiments the floating gate extends only over a part of the channel length which may be adjacent the source or drain or spaced from both, while the control gate extends at least over the rest of the channel, whereby, providing the latter is non-conductive, no source-drain current will flow in the absence of voltage on the control gate irrespective of the charge state of the floating gate. The control gate may completely overlap the floating gate or overlap it only partially either over or laterally of the channel, and the floating gate preferably has an extension running on thick insulation laterally of the channel to terminate on a 600 Š thick silica layer over the source or drain region allowing erasing current to flow to that region by any of the specific electrical mechanisms. Inter-gate capacitance may be increased, to permit use of lower operating voltages, by provision of a lateral extension of the control gate which overlies and is separated by thin insulation from the extension of the floating gate. Spacing of the floating gate from the drain and source reduces undesired capacitive coupling thereto and spacing enables the thickness of the gate insulation to be reduced to permit operation at reduced voltages. Various arrangements are described enabling the FETs in a matrix store to be individually programmed and erased individually, simultaneously, or row by row. |
