Adjacent pulse edges position control circuit - handles pulses whose spacing is shorter than minimum time interval

摘要

The two pulse edges belong to two rectangular pulses in a clock pulse controlled processing installation. Each rectangular pulse is applied to a flip-flop (TZF1, TZF2) controlled by cycle state. Their outputs (TZF13, TZF23) deliver corrected pulse edges to an EXCLUSIVE OR circuit (ER) which controls a circuit (SG) which releases a short pulse at positive and negative edges, applied through a NOR gate (ND) to the timing input (TFF12) of a clock pulse edge controlled flip-flop (TFF1). The output of the latter (TFF13) is connected to timing inputs (TZF12, TZF22) of the two flip-flops (TZF1, TZF2). Resetting output (TFF14) of the flip-flop (TFF1) is connected to its input (TFF11) and to resetting input (ZR1) of a counter (ZR) switched forward by the installation clock pulses.