发明名称 |
WAFER SCALE INTEGRATED DEVICE |
摘要 |
A system and method for interconnecting a plurality of separate memories (on other circuits) on a wafer so as to electrically exclude defective memories and include operative memories. A single discretionary connection is associated with each of the separate memories and such connection is made (or broken) after a memory is tested. In addition to a bidirectional memory bus used for input/output data and addresses, the wafer includes a separate identity bus used to define the memory organization. The identity bus is interconnected by a plurality of incrementers, one associated with each memory. The signal on the identity bus is incremented by useable memories and such signal is compared to an address on the bidirectional memory bus to select memories in an organized manner. |
申请公布号 |
JPS5231688(A) |
申请公布日期 |
1977.03.10 |
申请号 |
JP19760089276 |
申请日期 |
1976.07.28 |
申请人 |
INTEL CORP |
发明人 |
MERUSHIAN II HOTSUFU JIYUNIA |
分类号 |
H01L21/82;G06F12/06;G11C29/00;H01L21/8247;H01L29/788;H01L29/792 |
主分类号 |
H01L21/82 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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