| 摘要 |
A cache memory stores n parts of a main memory, and the main memory is constituted by N sets. Each set is constituted by a plurality of blocks. A memory unit is provided for storing address data of upper address portions each of which designates a memory set of data stored in an address in the cache memory. The address data are stored in an address in the memory device corresponding to the address in the cache memory. Both the addresses designate a memory block in the designated memory set. A validity unit is provided for storing validity bits for indicating a valid/invalid state of address data in each address of the memory unit. An initialization circuit is arranged to simultaneously invalidate the valid bits. Accordingly, the generation of an erroneous coincidence signal can be prevented, and a data reading operation from the memory device can be performed quickly and satisfactorily.
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