Divider for an electronic timepiece

摘要

A divider for an electronic timepiece comprises a multistage divider circuit having a plurality of 1/2 dividing stages connected in cascade. Logic circuitry connected to the first and last stages develops a preselected number of pulse signals smaller in number than the dividing number of the divider circuit to effect selective stopping of the counting of only one input signal pulse applied to the divider circuit to thereby obtain fine adjustment of the final output signal pulses.