SEMICONDUCTOR DEVICE HAVING ELECTRICALLY INSULATING BARRIERS FOR SURFACE LEAKAGE SENSITIVE DEVICES METHOD OF FORMING

摘要

1422586 Integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 1 June 1973 [30 June 1972] 26208/73 Heading H1K Laterial isolation of surface-leakage sensitive semiconductor circuit elements in an integrated circuit is effected by insulating barriers 18 extending through a P--type epitaxial layer 11 and into a P+-type substrate 10, the substrate 10 providing a common terminal for all the circuit elements. For a Si structure the barriers 18 are preferably of SiO 2 formed by selectively oxidizing part of the thickness of the epitaxial layer 11, etching the oxide so formed to provide grooves and oxidizing the material exposed in the grooves. The upper surface of the barriers 18 is preferably flush with that of the epitaxial layer 11. Amonst the devices which can employ this form of isolation are charge-coupled devices, field-induced capacitors, dynamic storage cells and dynamic logic cells using FETs. Fig. 11 (not shown) illustrates a pair of IGFETs, one having a metal gate (34) and the other a polycrystalline Si gate (19), located in adjacent islands of the epitaxial layer (11) and separated by an oxide barrier (18). Fig. 12 shows an IGFET having four channel regions 44, 43, 45, 47 in series, each beneath a corresponding gate electrode of which the first and third 42, 46 are of metal and the second and fourth 19 are of polycrystalline Si. Diffused source and drain regions 40, 41 abut the oxide barriers 18. Fig. 10 shows two adjacent memory cells in a memory array provided with diffused N+-type bit lines adjacent isolation barriers 18, and orthogonal Al ward lines 27. Each cell includes an IGFET constituted by a bit line 22 as source, a channel region 23 of the epitaxial layer 11, a Si 3 N 4 -on-SiO 2 gate insulation 16 and part of the ward line 27 as gate electrode. Charge conducted through the channel region 23 is stored in a capacitor constituted by a polycrystalline Si electrode 19, part of the insulation 16 and the underlying area 20 of the epitaxial layer 11. The polycrystalline Si electrode 19 is separated from the overlying Al ward line 27 by an oxide layer 24, and a similar layer isolates the ward line 27 from each bit line 22 except where contact is required to be made. The capacitor electrodes 19 may alternatively be made of a refractory metal. A method of manufacture using conventional planar processing steps is described.