发明名称 Analog multiplier using multitail cell
摘要 A two-quadrant multiplier for multiplying first and second signals, which can realize wide input voltage ranges at a low supply voltage such as 3 or 3.3 V, has a multitail cell. This multitail cell contains a pair of first and second transistors having differential input ends and differential output ends, a third transistor having an input end, and a constant current source for driving the pair and the third transistor. The first signal is applied across the differential input ends of the pair, and the second signal is applied in a single polarity (e.g., either a positive or negative polarity) to the input end of the third transistor. An output signal of the multiplier is a multiplication result of the first and second signals which is differentially derived from the differential output ends of the pair. At least one additional transistor may be provided, an input end of which is coupled with the input ends of the third transistor to be applied with the second signal. Two such multitail cells may be combined to form a four-quadrant multiplier for the first and second signals.
申请公布号 US5986494(A) 申请公布日期 1999.11.16
申请号 US19960720572 申请日期 1996.10.01
申请人 NEC CORPORATION 发明人 KIMURA, KATSUJI
分类号 G06F7/52;G06G7/163;H03F3/45;(IPC1-7):G06F7/52 主分类号 G06F7/52
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