发明名称 |
METHOD OF FABRICATING INJECTION LOGIC INTEGRATED CIRCUITS USING OXIDE ISOLATION AND THE RESULTING STRUCTURE |
摘要 |
<p>An integrated injection logic circuit cell structure and its fabrication are simplified. A pattern of oxide isolation regions is used to define, at least partially, the introduction of two types of impurities in such a way as to reduce the number of masking steps. Certain of these oxide regions do not penetrate through the conventional epitaxial layer, leaving a lateral buried path to serve as the base of a lateral injection transistor. A pattern of polycrystalline silicon containing impurities is used both as a diffusion source and an interconnection.</p> |
申请公布号 |
CA1005170(A) |
申请公布日期 |
1977.02.08 |
申请号 |
CA19740215537 |
申请日期 |
1974.12.09 |
申请人 |
WESTERN ELECTRIC COMPANY, INCORPORATED |
发明人 |
EVANS, WILLIAM J.;GRANT, WESLEY N.;MURPHY, BERNARD T. |
分类号 |
H01L29/73;H01L21/00;H01L21/285;H01L21/331;H01L21/762;H01L21/8222;H01L21/8226;H01L23/522;H01L27/00;H01L27/082;H01L29/06;H01L29/08 |
主分类号 |
H01L29/73 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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