| 摘要 |
A digital system is disclosed for demodulating relative phase-shift modulated binary data using a delay circuit to store one data bit period of sample bits for phase comparison with the next data bit period of sample bits, and a cascaded delay circuit of the same length to effectively repeat the demodulation one data bit period later. An up-down counter effectively integrates the difference between current demodulated sample bits and the demodulated sample bits of the previous data bit period to enhance data bit detection. Such data demodulation is used from a selected one of three channels, a center channel for no Doppler shift compensation, and two channels for positive and negative Doppler shift compensation. All delay circuits are implemented with random access memory units, and all units in each channel are addressed by a single counter preset each time it overflows in response to counting clock pulses to set the length of the delay circuits according to the average of any expansion or contraction of a data bit period expected due to Doppler shift.
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