ROBUST DELAY FAULT BUILT-IN SELF-TESTING METHOD AND APPARATUS

摘要

This invention relates to a method and apparatus for robust delay fault testing of integrated circuits (IC) (22) with built-in self testing. Hazardous nodes (28) of the IC (22) are determined. The topology of the IC (22) can be modified to include cut-point (23) at the hazardous nodes (28) of the circuit (22). Input (24) to the cut-point (23) is diverted to an observation point (30). A first output MISR (25) provides a signature for the outputs (27) of the IC (22). A cut-point multi-input signature register (MISR) (30) The observation point generates a first signature. During testing a hazard-free input pattern is applied to the IC (22) and the generated first and second signatures are compared to known correct signatures.