发明名称 BURST SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To correctly obtain the timing of data brought to multivalued FM demodulation even in the case there are many noises by detecting the receiving data obtained by a binary frequency modulation(FM) demodulator by a unique word(UW) detecting circuit. CONSTITUTION:A bit timing extracting circuit 4 outputs a clock 104 being a bit timing of receiving data 103. A binary FM demodulator 9 uses this clock 104 and executes a binary frequency demodulation from a signal 102, and outputs receiving data 106. A UW detecting circuit 5 detects a UW 202 of a burst signal 200 from in the receiving data 106, and outputs a timing signal 105 for showing the timing for starting the data 203. In such a way, even in the case there are many noises, the timing of data brought to multivalued FM demodulation can be obtained correctly, and the data can be demodulated correctly.
申请公布号 JPH03123136(A) 申请公布日期 1991.05.24
申请号 JP19890259961 申请日期 1989.10.06
申请人 NEC CORP 发明人 TAKADA KAZUHIRO
分类号 H04L27/14;H04L7/08 主分类号 H04L27/14
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