| 发明名称 |
PROCESS FOR COMPLEMENTARY INSULATED GATE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
| 摘要 |
PURPOSE:To make the density of integration higher and to avoid apperance of parasitic MOS by varying the concentration distribution of well region with a layer of epitaxial growth. |
| 申请公布号 |
JPS5214388(A) |
申请公布日期 |
1977.02.03 |
| 申请号 |
JP19750090291 |
申请日期 |
1975.07.25 |
| 申请人 |
HITACHI LTD |
发明人 |
MEGURO SATOSHI;AZUMA TAKASHI;FUKUDA HIDEKI;KUKI YASUKI |
| 分类号 |
H01L27/08;H01L21/76;H01L27/092;H01L29/78 |
主分类号 |
H01L27/08 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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