| 发明名称 |
SHIFT REGISTER DATA TRANSFER CONTROL SYSTEM |
| 摘要 |
PURPOSE:When there is some difference between the central processor unit bit transfer speed and that of the external memory unit, to reduce transfer time by harmonizing these speeds. |
| 申请公布号 |
JPS5214323(A) |
申请公布日期 |
1977.02.03 |
| 申请号 |
JP19750090421 |
申请日期 |
1975.07.24 |
| 申请人 |
NIPPON TELEGRAPH & TELEPHONE |
发明人 |
MISE KEISUKE;AMANO TSUNEO |
| 分类号 |
G06F5/08;G11C19/08 |
主分类号 |
G06F5/08 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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