On chip bias temperature instability characterization of a semiconductor device

摘要

Embodiments of the present invention provide a circuit and method to characterize the impact of bias temperature instability on semiconductor devices. The circuit comprises a transistor having a gate, drain, source, and body terminal. Two AC pad sets each having a plurality of conductive pads. Two DC pads are in communication with a DC supply and/or meter. The gate terminal is in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets. The drain terminal is in communication with a second conductive pad of an AC pad set and the source terminal with a second conductive pad of another AC pad set. One DC pad is in communication with the gate terminal through a first serial resistor and another DC pad with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals.

主权项

1. A circuit comprising:
a transistor having a gate, drain, source, and body terminal; two AC pad sets, wherein each pad set includes a plurality of conductive pads; two DC pads configured to be in communication with a DC power supply or meter; and wherein: the gate terminal is configured to be in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets; the drain terminal is configured to be in communication with a second conductive pad of an AC pad set; the source terminal is configured to be in communication with a second conductive pad of another AC pad set; one DC pad is in communication with the gate terminal through a first serial resistor and another DC pad is in communication with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals; and a plurality of switches are configured to allow for radio frequency (RF) stressing and RF characterization of the transistor without modifying a setup of the AC pad sets and the DC pads, wherein at least one of the plurality of switches is connected to a bias tee that restricts a DC bias.