| 摘要 |
PURPOSE:To improve the test efficiency of a logic circuit by writing or reading data with only the flip-flop circuit that is optionally selected out of those flip- flop circuits which form a shift register with a scanning path method. CONSTITUTION:A scan address generating circuit 17 outputs the address signals to the scan-out switching circuits 11 - 13 provided on the data read-only flip-flop circuits 5 - 7. Thus the output terminals of the circuits 5 - 7 are connected to a scan-out terminal. Then the output of a logic circuit 1 is directly given to the scan-out terminal even with no input of a scanning clock. Simultaneously, the scanning clocks are inputted to the scanning clock control circuits 14 - 16 connected to the circuits 5 - 7 together with the address signals 18 - 20 which are selectively outputted from a scanning address circuit. Thus, the test data can be set to only the flip-flop circuit that is specified by the address signals 18 - 20. Thus, the test effect of the circuit 1 is improved. |
