| 摘要 |
PURPOSE:To perform analysis in various kinds of aspects by using the heirarchical description of a module by describing a work content and required information, material, and man-hours, etc., in the module in hierarchical fashion, and attaching information with respect to transport delay on the input/output terminal of the module. CONSTITUTION:A development analytic data 6 is generated with a production schedule department in the same period when a developing design 1 is delivered to a circuit design 2, and an experimental schedule 7 is generated at a experimental department, and a design experimental request sheet 8 is issued to an experimental site. The experimental preparation 9 of the LSI is started when the request sheet 8 is already distributed, or the design 5 of a block is finished and registered, and also, a layout design 3 is prepared, and a design result is checked. In comparison with a conventional PART diagram, only an AND logic diagram not outputted until all input are completed is outputted in the conventional PART diagram, while, the compound logic diagram of AND and OR can be expressed in the method, and it is possible to easily realize to weight the input, etc., by defining the function of a cell in functional descriptive language. |
