| 摘要 |
PURPOSE:To solve the problem points of an open collector buffer and a 3-state buffer by combining the 3-state buffer and a delaying circuit to constitute a buffer circuit of two terminals. CONSTITUTION:A delaying circuit 5 delays a signal inputted to an input 51 by a prescribed time (td) and outputs it to its output 52. When the time varied from L to H at a state that an output 42 of a 3-state buffer 4 is enable (when a control input 45 is '0') is denoted as toLH, the delay time of the delaying circuit 5 becomes larger than toLH. Accordingly, in the case a signal A1 varied as 1 0 1 is inputted to the input terminal 2 of a buffer circuit 1, the output 42 of the 3-state buffer 4 is not varied from L to Hi-Z but varied as L H Hi Z so that H always enters between L and Hi-Z (high impedance). In such a way, defects of both the 3-state buffer and the open collector buffer are solved. |
