| 摘要 |
<p>PURPOSE:To generate an N-fold period clock at the part of a logical circuit by generating the N-fold period clock having other phase using two phases of the whole phases of a basic clock and the phases of the N-fold period clock and subtracting the supply number of the N-fold period clocks. CONSTITUTION:A timing and a period when a basic stage signal K20 comes to a high level is decided by an exclusive OR at the timing of clocks T20 and T24 irrespective of the initial values of one bit counters CNTA and CNTB. Shift stage signals K21-K27 which are obtained by sequentially shifting the phases by one phase difference of the basic clock CLK by FF21-27 are generated based on the signal K20. An AND part 13 receives the total phase stage signals STG consisting of the signals K20-K27 and the basic clocks T0-T3. Consequently, respective AND circuits A20-A27 take the AND of two input signals and generate output two-fold period clocks T20-T27.</p> |
