| 摘要 |
PURPOSE:To eliminate the need for a special bias circuit and to minimize the gain reduction by introducing each of two outputs of a 2nd stage differential amplifier to each base of a couple of transistors(TRs) of a 3rd stage differential amplifier respectively as a balanced input. CONSTITUTION:When an emitter voltage of a TR Q14 rises due to offset, a change is caused in two outputs of a 2nd stage differential amplifier (b) and a base voltage of a TR Q6 rises, while the base broadcast of a TR Q7 is decreased. Thus, a base voltage of a TR Q8 of a 3rd stage differential amplifier (c) is decreased, while a base voltage of a TR Q9 is increased and similarly a base voltage of a TR Q12 of a 4th stage differential amplifier (d) is decreased and a base voltage of a TR Q13 rises. As a result, an emitter voltage of the TR Q14 is decreased to suppress the offset. Thus, a special bias circuit is not required and the gain reduction is minimized. |
