发明名称 Memory array with readout isolation
摘要 Methods and apparatus for providing an array of passive nonlinear elements having an interface circuit that isolates the array from loading effects from external connections to the array. In one embodiment, a capacitive switching circuit is used to electrically isolate the elements in the array from the external load.
申请公布号 US7548453(B2) 申请公布日期 2009.06.16
申请号 US20070729323 申请日期 2007.03.28
申请人 CONTOUR SEMICONDUCTOR, INC. 发明人 NESTLER ERIC
分类号 G11C11/36 主分类号 G11C11/36
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