发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH CPU PART AND PERIPHERAL PART
摘要 PURPOSE:To conduct an efficient test by providing a means which separates a clock for putting the CPU part in operation and a clock for placing the peripheral part in operation with a signal which is inputted to one mode switching terminal (test terminal). CONSTITUTION:When the test terminal 8 is at 'L' level, the device is in a normal use state and selectors 11 and 12 supply clocks to the CPU part 6 and peripheral part 7 from an oscillation part 5. The test terminal 8 is set to 'H' level and then the selectors 11 and 12 are switched to supply the clock of the CPU part 6 from an input terminal 9 and the clock of the peripheral part 7 from an input terminal 10. Consequently, the CPU part 6 and peripheral part 7 operate individually and a redundant test pattern wherein the CPU part 6 and peripheral part are matched in cycle is not necessary, so that the test is conducted efficiently.
申请公布号 JPH04100160(A) 申请公布日期 1992.04.02
申请号 JP19900217727 申请日期 1990.08.18
申请人 SEIKO EPSON CORP 发明人 AKIYAMA CHISATO
分类号 G01R31/28;G06F1/04;G06F11/22;G06F15/78 主分类号 G01R31/28
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