| 摘要 |
PURPOSE:To identify generated error information on the stage of an error processing at a CPU in the manner of a program by storing an error address at that time in a memory address, which is set to an address register for storage in advance, when ECC error (data error) is generated when reading a memory. CONSTITUTION:In a memory read cycle, the ECC error is detected at timing t17 and when an ECC error signal 9 is made significant, a data signal 16 and a write signal 19 are outputted and respectively delayed for one clock by delay circuits 17 and 20. A data signal 18 and a write signal 21 are formed as data at timing t19, a selector circuit 22 selects an address signal 15 at the timing t17, a selector circuit 23 selects an address signal 15 at the timing t17, and the selector circuit 23 selects the data signal 18 at the timing t17. Therefore, the error address outputted to a data signal 25 is written in the storage address at rise timing t23 of a write signal 21. Thus, the state of generating the ECC error can be identified on the stage of the error processing in the manner of the program. |
