发明名称 |
REDUCTION OF SHEET RESISTANCE OF PHOSPHORUS IMPLANTED POLY-SILICON |
摘要 |
There is a process for reducing the sheet resistance of phosphorus-implanted polysilicon. In an example embodiment, there is an MOS transistor structure (300). The structure has a gate region, drain region and a source region. A method (220) for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon (221) at a predetermined temperature onto the gate region. An amorphizing species is implanted (222) into the intrinsic amorphous silicon. Phosphorus species are then implanted (223) into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species. |
申请公布号 |
WO2006035411(A3) |
申请公布日期 |
2006.09.08 |
申请号 |
WO2005IB53208 |
申请日期 |
2005.09.28 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS, N.V.;U.S. PHILIPS CORPORATION;EUEN, WOLFGANG;GROSS, STEPHAN |
发明人 |
EUEN, WOLFGANG;GROSS, STEPHAN |
分类号 |
H01L21/28;H01L21/265;H01L21/3215;H01L29/49 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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