发明名称 Jitter suppression circuit
摘要 In a circuit suppressing jitters without a synchronizing clock signal and an increase of a circuit scale, input data is regenerated by a data regeneration circuit in a broadband, a predetermined signal pattern which generates phase deviations exceeding a predetermined value is detected from the data regenerated by the data regeneration circuit by a pattern detection circuit, a reverse phase deviation signal having reverse phase deviations of phase deviations corresponding to the predetermined signal pattern is generated by a reverse phase deviation generating circuit, and an output signal of the data regeneration circuit is canceled by a phase deviation correcting circuit with the reverse phase deviation signal.
申请公布号 US2008069282(A1) 申请公布日期 2008.03.20
申请号 US20070898983 申请日期 2007.09.18
申请人 KUWATA NAOKI 发明人 KUWATA NAOKI
分类号 H03D3/24 主分类号 H03D3/24
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