Method for chip package

摘要

Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.

主权项

1. A method for chip package, comprising:
providing a semi-packaged wafer, the semi-packaged wafer having a dicing street and a metal pad; selectively forming a metal electrode on the metal pad; forming a protective layer in area outside the metal electrode on the wafer, the protective layer covering the dicing street, where the protective layer is made of a cured thermosetting epoxy resin comprising a solidified filler which has a particle diameter less than one third of the thickness of the thermosetting epoxy resin before the thermosetting epoxy resin is cured, and wherein the solidified filler has a particle diameter greater than one third of the thickness of the thermosetting epoxy resin after the thermosetting epoxy resin is cured, and wherein the solidified filler is silica solid particles; forming a solder ball on the metal electrode; and dicing the wafer along the dicing street.