LOGIC SYSTEM INCLUDING AN EMITTER-FOLLOWER AMPLIFIER HAVING A TWO-TERMINAL CURRENT-LIMITING DEVICE CONNECTED BETWEEN ITS EMITTER ELECTRODE AND A POINT OF REFERENCE POTENTIAL,申请号USD3458718-传众专利搜索

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发明名称	LOGIC SYSTEM INCLUDING AN EMITTER-FOLLOWER AMPLIFIER HAVING A TWO-TERMINAL CURRENT-LIMITING DEVICE CONNECTED BETWEEN ITS EMITTER ELECTRODE AND A POINT OF REFERENCE POTENTIAL
摘要
申请公布号	US3458718(A)	申请公布日期	1969.07.29
申请号	USD3458718	申请日期	1966.03.17
申请人	BELL TELEPHONE LAB. INC.	发明人	MATTHEW F. SLANA
分类号	H03K19/09;(IPC1-7):H03K19/08	主分类号	H03K19/09
代理机构		代理人
主权项
地址

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