发明名称 |
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF |
摘要 |
PURPOSE:To enable wiring resistance to be reduced and a memory cell area to be reduced by placing a conductive film which fixes a source potential of a MOS transistor for drive at a reference potential on an upper part than the MOS transistor after covering an entire surface of the memory cell. CONSTITUTION:MOS transistors for driving an n channel T1 and T2 and MOS transistors T3 and T4 for transferring the n channel are formed within a p-type well 24 which is formed within an n-type silicon substrate 23. A connection hole 14c is opened on a high-concentration n-type impurities region 12c which becomes a common source of the MOS transistors T1 and T2. A second-layer conductive film 15c for fixing a source potential of all MOS transistors for drive within the memory cell is connected to the region 12c through the connection hole 14c, thus enabling a memory cell area to be reduced while reducing resistance of wiring resistor of the conductive film for fixing the source potential to the reference potential. |
申请公布号 |
JPH04162668(A) |
申请公布日期 |
1992.06.08 |
申请号 |
JP19900287058 |
申请日期 |
1990.10.26 |
申请人 |
HITACHI LTD;HITACHI VLSI ENG CORP |
发明人 |
YAMANAKA TOSHIAKI;HASEGAWA NORIO;TANAKA TOSHIHIKO;HASHIMOTO KOJI;ISHIBASHI KOICHIRO;HASHIMOTO NAOTAKA;SHIMIZU AKIHIRO;SUGAWARA YASUHIRO;KURE TOKUO;IIJIMA SHINPEI;NISHIDA TAKASHI;TAKEDA EIJI |
分类号 |
G03F1/29;G03F1/30;G03F1/68;H01L21/027;H01L21/8244;H01L27/11 |
主分类号 |
G03F1/29 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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