| 摘要 |
PURPOSE: A device for preventing cache aliasing in writing operation using translation look ahead buffer prediction bit is provided so that a cache capability can be enhanced and an exact segment prediction is maintained by removing the possibility of aliasing in cache writing operation. CONSTITUTION: A device for preventing cache aliasing in writing operation using translation look ahead buffer prediction bit includes a CPU(20). The CPU(20) executes a command and processes data according to the implemented technology. Generally, the most effective unit exchanging data and commands between the CPU(20) and a memory(54) is to use an on-chip cache(24). When the CPU(20) reads a word from the first cache(24A), the CPU(20) generates a virtual address(VA), for example, VA£41:0|. The virtual address(VA) includes a page index, for example, VA£41:14| and an offset, for example, VA£13:0|. Here,£x:y| is a naming method for representing bit positions x and y at the data word or address word. The page index includes information on the physical address to be accessed. The offset represents a block(25A) of the first cache(24A) to be accessed.
|
