CLOCK GENERATING CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS

摘要

PROBLEM TO BE SOLVED: To provide a clock generating circuit of a semiconductor memory apparatus capable of preventing the transition timing of a rising clock signal and a falling clock signal from deviating from each other due to variation in P.V.T. and a long transmission distance.

SOLUTION: A clock generating circuit of a semiconductor memory apparatus includes a phase splitter that delays a clock to generate a delayed clock and inverts the clock to generate an inverted clock, and a clock buffer that buffers the delayed clock and the inverted clock and outputs them as a rising clock and a falling clock.

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