发明名称 Zero frame buffer
摘要 Circuits, methods, and apparatus that allow the elimination of a frame buffer connected directly to a graphics processing unit. The graphics processing unit includes an on-chip memory. Following system power-up or reset, the GPU initially renders comparatively low-resolution images to the on-chip memory for display. Afterward, the GPU renders images, which are typically higher resolution, and stores them in a system memory, apart from the graphics processing unit. The on-chip memory, which is no longer needed for image storage, instead stores address information, referred to as page tables, identifying the location of data stored by the GPU in the separate system memory.
申请公布号 US7483032(B1) 申请公布日期 2009.01.27
申请号 US20050253438 申请日期 2005.10.18
申请人 NVIDIA CORPORATION 发明人 YEOH SONNY S.;KEIL SHANE J.;MA DENNIS K.;TONG PETER C.
分类号 G06F12/00;G06F12/08;G06F15/16 主分类号 G06F12/00
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