| 摘要 |
PURPOSE:To minimize an error rate at data extraction without using a delay line or the like for the adjustment. CONSTITUTION:An input data Din is fed to a timing circuit 2, from which a timing pulse Pt is obtained. The pulse Pt and a noninverting oscillation output Po+ of a VCO 5B are compared by a phase comparator 4 and its error voltage is fed to the VCO 5B as a control voltage via a low pass filter 6 and a DC amplifier 7. The input data Din is fed to a DFF 3 via a delay circuit 8 and a data Dout is extracted by using an inverting oscillation output Po- of the VCO 5B as a clock CK. The duty ratio of the oscillating outputs Po+, Po- is varied by adjusting a slider of a variable resistor VR1 of the VCO 5B to adjust the extraction timing. The error rate at extraction is minimized without use of a delay line or the like. |
