发明名称 A power-on reset circuit.
摘要 <p>A power-on reset circuit which resets internal circuits of a semiconductor device such as a microprocessor initially after an operating voltage is switched on to the internal circuits via an operating voltage terminal (Tc) comprising a capacitance circuit (C), a detector means (I1, I2, I3) for detecting the potential of the capacitance circuit (C) and outputting a reset signal (R) to the internal circuits until the potential on the capacitance circuit (C) reaches a predetermined value. The power-on reset circuit also comprising a resistor circuit (RCT) connected between one of the terminals (Tc) of the capacitance circuit (C) and the operating voltage terminal (Tp), the resistor circuit (RCT) consisting of a first resistor element (R min 1) and a second resistor element (R2) connected in parallel with the first resistor element (R min 1). The second resistor element (Ra) has a resistance the value of which reduces after the potential of the capacitance circuit (C) has reached the predetermined value. This change in resistance of the second resistor element (R2) ensures that the reset signal (R) is output from the detector means (I1, I2, I3) for a sufficient time to reset all the internal circuits of the semiconductor device even if the operating voltage (VDD) applied to the operating voltage terminal (Tc) only builds up slowly.</p>
申请公布号 EP0035345(A1) 申请公布日期 1981.09.09
申请号 EP19810300666 申请日期 1981.02.18
申请人 FUJITSU LIMITED 发明人 MONMA, HIDEO;TAKAHASHI, MASAYUKI
分类号 G06F1/24;H03K3/356;H03K17/22;(IPC1-7):03K17/22;06F1/00 主分类号 G06F1/24
代理机构 代理人
主权项
地址