CONNECTION FOR TWO-PORT MEMORY CONTROLLER

摘要

The design concerns the connection of the dual port memory controller for multiprocessor and multi-computer systems. It handles the problem of fast and collisionless switching of access to memory cells from both ports in program controlled allocation of memories only for one port by blocking the other port. The problem is handled in the way that the data, address and control command are connected to the memory by means of the data, address and command amplifiers, which are controlled by the sequence of pulses from shift registers, flip-flop circuits and address decoders so that the memory would be at disposal only to the single port in one instant of time. The controller consists of the decoders (100, 101), coincidence port (102), R reset-set flip-flop circuits (103, 108, 109), D-type flip-flop circuit (106), and also of the shift registers (104, 105) of write command, data, and address amplifiers (110, 111, 112, 113, 114), data selection decoder (118) and interrupt indicators (116, 117).<IMAGE>