发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To prevent the frequency jump of an oscillation frequency and to prevent the oscillation frequency of a voltage controlled oscillator from being fluctuated by the fluctuation of a power supply voltage. CONSTITUTION:When an input clock signal 101 is interrupted, as a signal to compare the phase at a phase comparator circuit 4, an oscillation signal 108 of an oscillator 7 is passed through an M (M=6N) frequency divider circuit 8 in place of the output signal of an L frequency divider circuit 10, and an alternate comparative signal 111 obtained by comparing the phase with that of the output signal from the L frequency divider circuit 10 in a phase comparator circuit 9 is used. The M frequency divider circuit 8 outputs a signal 110 frequency dividing the oscillation signal 108 of the oscillator 7 into M (M=6N) frequency divisions and a signal 109 frequency dividing it into N frequency divisions. While using the signals 109 and 110 from the M frequency divider circuit 8 and a signal 107 from the L frequency divider circuit 10, the phase comparator 9 executes a phase comparing operation.
申请公布号 JPH04365223(A) 申请公布日期 1992.12.17
申请号 JP19910142003 申请日期 1991.06.13
申请人 NEC CORP;NEC SHIZUOKA LTD 发明人 KADOWAKI MAKOTO;KIMURA KIMIHIKO
分类号 H03L7/14 主分类号 H03L7/14
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