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发明名称
记忆晶胞电容与逻辑元件之整合制造方去及其结构
摘要
一种记忆晶胞电容与逻辑元件之整合制造方法及其结构。在本方法中,形成第一导电层与第二导电层分别位于半导体基材上之逻辑区与记忆晶胞区中。形成第一光阻层覆盖逻辑区,并暴露邻接于记忆晶胞区中之第二导电层的内金属介电层。蚀刻移除内金属介电层之暴露部分,以形成一开口邻接于第二导电层。形成电容介电层于上述开口之数个内壁上,以建构金属–绝缘–金属(MIM)电容。
申请公布号
TW200631094
申请公布日期
2006.09.01
申请号
TW094140814
申请日期
2005.11.21
申请人
台湾积体电路制造股份有限公司
发明人
涂国基
分类号
H01L21/31;H01L21/76
主分类号
H01L21/31
代理机构
代理人
蔡坤财
主权项
地址
新竹市新竹科学工业园区力行六路8号
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