发明名称
摘要 PURPOSE:To increase the degree of multiplication in a vector processing mode by replacing the orders of DO loops in a source program as much as possible and integrating plural DO loops into a single loop. CONSTITUTION:A unitable DO loop detecting part 161 checks the DO loops in a group A to detect those loops having the same vector length VL, that is, a DO1 and a DO3 having the VL=100. These two loops are identified in a pair. An executing order relation detecting part 162 checks the presence or absence of the executing order relation with each DO loop in the group A. Here the executing order relation is shown by a double arrow head line and therefore the executing order relation is confirmed between both loops DO1 and DO2. A DO loop replacing part 163 moves the DO3 under the DO1 so that the unitable DO loops are set adjacent to each other. At the same time, the loop DO2 that should be executed after the loop DO1 is moved under the DO3. Thus it is possible as shown in a group B to unite both loops DO1 and DO3 together without breaking the executing order relation among those DO loops.
申请公布号 JPH053030(B2) 申请公布日期 1993.01.13
申请号 JP19860004742 申请日期 1986.01.13
申请人 FUJITSU LTD 发明人 SAGAWA MORIE;AOKI MASAKI;NAGAKURA HIROSHI
分类号 G06F17/16;G06F15/78 主分类号 G06F17/16
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