摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of restraining delay time variations of clock signal caused from the noise of a power supply voltage. SOLUTION: A power supply for a clock buffer cell 2 and a sub-clock buffer cell 4 which distribute the clock signal of a circuit 1 is separated from other power supplies, and power is supplied from a special power supply wiring 6. Thereby, the effects of power supply noise generated from operation of other circuits can be reduced, such as an input/output interface cell on the buffer cells 2 and 4. Delay time variations of the buffer cells 2 and 4 are restrained, and jitters of a clock signal system can be reduced.</p> |