| 摘要 |
PURPOSE:To eliminate the omission of data due to the refreshing period with one RAM by performing the writing or reading of two data in one time slot and performing the refreshing by next one time slot. CONSTITUTION:From a control signal generating part 3, a control signal (a) to repeat an H level and an L level or each one time slot (TS) and a control signal (b) to repeat the L level and the H level for each one TS are generated, and inputted to a memory control part 4. Thus, from a memory control part 4 to a DRAM 1, an address (ADR), a row address external clock signal (RAS) for writing and a column address external clock signal (CAS) for writing are imparted. Then, when the signal (a) is an L level, the writing of the data from a data input output part 2 is performed, and when the signal (b) is the L level, the refreshing is performed. That is, two data to be over two TSs in the one TS are written, and in the next one TS, the refreshing is performed. |
