CLOCK TREE DESIGN METHODS FOR ULTRA-WIDE VOLTAGE RANGE CIRCUITS

摘要

Clock tree design methods for ultra-wide voltage range circuits are disclosed. In one aspect, place and route software creates an integrated circuit (IC) in an optimal configuration at a first voltage condition. A first clock tree is created as part of the place and route process. Clock skew for the first clock tree is evaluated and minimized through insertion of bypassable delay elements. The delay elements are then removed from the wiring routing diagram. A second voltage condition is identified, and clock tree generation software is allowed to optimize the wiring routing diagram for the second voltage condition. The second clock tree generation software may insert more bypassable delay elements into the wiring routing diagram that allow clock skew optimization at the second voltage condition. The initial bypassable delay elements are then reinserted into the wiring routing diagram and a finished IC is established.

主权项

1. A method of designing an integrated circuit (IC), the method comprising:
identifying circuit elements within an IC; under a first voltage constraint, using first place and route software operating to create a first clock tree diagram and a wiring routing diagram for the circuit elements within the IC including providing first bypassable delay elements as appropriate within a first clock tree; removing the first bypassable delay elements from the first clock tree diagram and the wiring routing diagram; under a second voltage constraint, using second clock tree generation software to create a second clock tree diagram for the circuit elements within the IC including providing second bypassable delay elements; and in the wiring routing diagram, reinserting the first bypassable delay elements to form a completed wiring routing diagram.