| 摘要 |
PURPOSE:To improve the interchangeability between a device and a recording medium by delaying the start of a synchronous operation for a reproducing signal for the prescribed time from the head of a storing region and generating the correct synchronous clock for the reproducing signal surely in a storage region. CONSTITUTION:A counter 20 counts a clock while making a sector arc detection signal S1 detected by a SM detecter 1 as a reference point, the detecting position is delayed e.g. by one byte from the head position of the pattern of the counter 3 while considering variation factors. The detection signal S10 from the counter 20 is sent to a circuit for generating PLL gate signal 7 and the PLL gate signal S11 is generated. Since the head position detection signal S10 is outputted while delaying by one byte, the signal S10 rises while delaying by one byte. Consequently, the synchronous operation for the reproducing signal in the synchronous clock generating circuit 8 is started while delaying by one byte without fail. Thus, the operation is not locked to the other frequency. |
