| 摘要 |
PROBLEM TO BE SOLVED: To keep an internal clock stably even when another external input clock is selected. SOLUTION: Dummy 8k clock generating circuits 2-4 frequency-divide a 16M clock signal to generate a phase comparison use 8k clock signal so as to synchronize the phase comparison use 8k clock signal with an external 8k clock signal in a simulating way by resetting the frequency division action in a trailing timing of the external 8k clock signal. For example, when a selection input is switched to an input 2 on the occurrence of a fault of an input IN 1, the dummy 8k clock generating circuit 2 stops resetting and an input selection circuit 10 provides the output of the external 8k clock signal from the input IN 2 and the 8k clock signal from the clock generating circuit 2, a frequency control voltage in response to the phase between both the clock signals is generated by a phase comparator circuit 11 and a low pass filter(LPF) 12 and a voltage controlled oscillator(VCO) 13 adjusts an oscillating frequency of the 16M clock signal depending on the frequency control voltage. |
