| 摘要 |
Following data writing into a memory cell array according to an internal address signal, the data read out from each memory cell is compared with expected value data in a readout operation. A row decoder selects a plurality of memory cells belonging to the same row in the memory cell array at one time according to an address signal. A BIST circuit determines that repair is to be carried out with a spare memory cell row, not a spare memory cell column, when a plurality of defective memory cells are detected from the plurality of memory cells selected at one time.
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