Cross-coupled thyristor SRAM circuits and methods of operation

摘要

A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.

主权项

1. In an integrated circuit having at least one logic circuit operating within a MOSFET logic circuit range and a plurality of memory cells arranged in an array interconnected by a plurality of complementary bit line pairs and a plurality of word lines, each memory cell comprising:
a pair of cross-coupled thyristors, each thyristor having an anode and a cathode connected directly to a complementary bit line pair and a word line in a cross point arrangement; and each thyristor having regions electrically biased so that voltage swings on the complementary bit line pair and the word line, operating within a magnitude of the MOSFET logic circuit range, are sufficient to read and write the memory cell.