| 摘要 |
<p>1423909 Memory cells RCA CORPORATION 16 March 1973 [24 March 1972] 12752/73 Heading H3T An arrangement, e.g. an array of memory cells, comprises a memory cell M 11 having a first point Q coupled via the conduction path of at least one transistor X 11 b, Q 1 b to a first conductor 1, a second point #Q coupled via the conduction path of at least one transistor X 11 a, Q 1 a to a second conductor 2 and a clamping arrangement R 1 , R 2 wherein, when in operation the logical levels at Q, #Q are such that the transistors X 11 b, Q 1 b operate in a common source mode and transistors X 11 a, Q 1 a operate in a source follower mode and the conductor 1 is clamped to the potential level at Q, the clamp R 1 , R 2 responsive to the potential on conductor 1 clamps the conductor 2 to a reference potential. In operation, write in is achieved by enabling FET 201 and the selected one of the FETs 202b, 202a depending on whether a "1" or a "0" is to be written in as well as enabling the relevant addressing FETs X 11 a, X 11 b, Q 1 a, Q 1 b for the selected cell. For read-out, the same addressing transistors are enabled. With a logical level of "0" at #Q, FETs Q 1 a, X 11 a operate in a source follower mode and their gate source thresholds must be exceeded before they are rendered conductive i.e. the sense line 2 is not clamped to the low potential at #Q but has a high voltage level which may exceed the threshold voltage of I 1 in the sense amplifier S 2 to turn it on erroneously while the sense amplifier S 1 is turned on by the correct "1" level at Q. However the clamp R 1 , R 2 detects the presence of a high level at one of the sense lines to clamp the other to earth potential. Further FETs D 1 A, D 1 B, D 2 A, D 2 B, D 1 S, D 2 S may be used in addition to set the digit lines and sense lines to zero potential before a read or write-in. Fig. 2 (not shown) is a simplified version of the arrangement including a single memory cell.</p> |
