| 摘要 |
PURPOSE:To facilitate an easy change of design and also to vary the number of bits of the digital signals that can be produced within a fixed time, by varying the period of the clock signal used to convert the analog signals into the digital signals. CONSTITUTION:A 1/2 divider 9 which reduces the frequency of the master clock signal down to 1/2 is provided at the preceding stage of a divider 10. The clock signals impressed to a sequential comparison register 3 are used as the master clock signal or the output signal of the divider 9 through a multiplexer 12. The sampled input analog signal is converted into a digital signal by a sequential comparison type A/D converter after a three state buffer 4 is activated. The clock terminal CK of the register 3 requires (n) pieces of clocks during conversion into a digital signal of (n) bits. These clocks can be obtained from the output of the divider 9 by setting a multiplexer 12 at the (n) side. |
