| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the cost for testing by reducing the testing time for a load control variable delay circuit and a logic integrated circuit device or the like including it. SOLUTION: In a variable delay circuit VDL 1 of a load control including NAND gates NA1-NA3 where one of input terminals of each gate is selectively connected to a prescribed internal node n1 via transfer gates G1-G3 that receive an effective level of, e.g. corresponding bits of delay control signals DC1-DC3 and are made selectively conductive, the other input terminal of each of the NAND gates NA1-NA3 receives the corresponding bits of the delay control signals DC1-DC3. The variable delay circuit VDL1 is also provided with a 4- input NAND gate NA4 whose 1st to 3rd input terminals receive corresponding output signals from the NAND gates NA1-NA3 respectively and whose 4th input terminal receives a test control signal TE. An output signal, that is, a test output signal TO of the NAND gate NA 4 is used to conduct a function test of the variable delay circuit VDL1.</p> |
