发明名称 ARCHITECTURE FOR VECTOR MEMORY ARRAY TRANSPOSITION USING A BLOCK TRANSPOSITION ACCELERATOR
摘要 A system and method for vector memory array transposition. The system includes a vector memory, a block transposition accelerator, and an address controller. The vector memory stores a vector memory array. The block transposition accelerator reads a vector of a block of data within the vector memory array. The block transposition accelerator also writes a transposition of the vector of the block of data to the vector memory. The address controller determines a vector access order, and the block transposition accelerator accesses the vector of the block of data within the vector memory array according to the vector access order.
申请公布号 US2016170936(A1) 申请公布日期 2016.06.16
申请号 US201615049255 申请日期 2016.02.22
申请人 ST-ERICSSON SA, EN LIQUIDATION 发明人 Sun Yanmeng;Hu Liangliang
分类号 G06F15/80;G06F7/78;G06F9/30;G06F17/16 主分类号 G06F15/80
代理机构 代理人
主权项 1. A system for vector memory array transposition, the system comprising: a vector memory to store a vector memory array; a block transposition accelerator coupled to the vector memory, the block transposition accelerator configured to firstly read vectors of a block of data by shifting the vectors into the vector memory array along a first dimension such that each vector is shifted serially into the vector memory in the same direction as the first dimension and to secondly write a transposition of the vectors by shifting the transposition of the vectors out of the vector memory along a second dimension such that each transposed vector is shifted serially out of the vector memory in the same direction as the second dimension, wherein the second dimension is perpendicular to the first dimension in the vector memory array; an address controller coupled to the block transposition accelerator, the address controller configured to determine a vector access order, wherein the block transposition accelerator is configured to access the vector of the block of data within the vector memory array according to the vector access order; and wherein the vector memory is partitioned into a set of blocks comprising the block of data and the second block of data, and wherein each block of data of the set of blocks has a uniform block size.
地址 Plan-les-Ouates CH