发明名称 PROGRAM LOAD SYSTEM
摘要 PURPOSE:To eliminate the need for a long time for program load by dividing a program to be loaded, assigning a lead wire or a channel to each of each part and performing it in parallel with the program load. CONSTITUTION:A main controller 2-1 is connected to plural slave controllers 2-2, 2-3 via a time division multiplex highway outgoing line 2-4 and an incoming line 2-5. One channel is assigned among the controllers 2-1, 2-2 and 2-3 and other plural channels (not shown) are assigned to general terminal devices. A program of a memory 2-7 is divided into N (in the figure N=4) by a microcomputer 2-6 as No.0-No.3, four highways are occupied via a highway interface 2-8, transmitted in parallel with the slave controllers 2-2, 2-3 and stored in the memory section 2-7 via each highway interface 2-8. Thus, the time required for the program load is decreased to 1/4.
申请公布号 JPS60102041(A) 申请公布日期 1985.06.06
申请号 JP19830209068 申请日期 1983.11.09
申请人 HITACHI SEISAKUSHO KK 发明人 MORITA TAKASHI;AMADA EIICHI
分类号 G06F15/177 主分类号 G06F15/177
代理机构 代理人
主权项
地址