| 摘要 |
A combined ECL-to-TTL translator and decoder circuit consumes less power and has improved speed over prior art translator-decoder circuits. Low power consumption occurs since current does not flow appreciably through the combined translator-decoder circuit when its corresponding decoded output line is not selected. The combined circuit is faster than prior art translator-decoders due to reduced circuitry. The circuit includes a pair of transistors connected in series, a pair of transistors connected in parallel, and a pair of transistors connected as a current mirror.
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