Segment-erasable flash EPROM

摘要

A segment-erasable flash EPROM array formed in a silicon substrate of P-type conductivity comprises a layer of gate oxide formed on the silicon substrate. A first layer of polysilicon is formed on the gate oxide. A layer of oxide/nitride/oxide composite is formed on the first polysilicon layer. The ONO and underlying Poly1 define a plurality of parallel strips. N-type dopant introduced into the silicon substrate between the ONO/Poly1 strips define buried N+ bit lines. Alternate buried N+ bit lines have additional N-dopant introduced thereto to define graded source lines that alternate with buried N+ drain lines. Each of the graded source lines is contacted only at a plurality of EPROM cells sharing that graded source line such that the EPROM array is subdivided into a plurality of segments. The alternate drain lines are uncontacted. A plurality of Poly2 word lines are formed perpendicular to the ONO/Poly1 strips such that the intersection of the Poly2 word lines and the Poly1 strips define the location of a cross-point EPROM cell of the array. Each segment of the array include first and second Poly2 select lines, the intersection of which with the Poly1 defines first and second select transistors such that each buried N+ drain lines is electrically connectable to one of its adjacent graded source lines via the first select transistor and to the other adjacent graded source line via the second select transistor. Finally, each segment also includes segment select lines that define the gate of a segment select transistor associated with each end of the graded source line.